Generally, constant voltage circuits have an output node connected to a high-capacity capacitor and therefore have high inrush currents for charging the capacitor when the constant voltage circuits are turned on. Very high or long-lasting inrush current may cause performance degradation of an output transistor and, sometimes, failure of the output transistor. To circumvent these problems, circuits for reducing inrush current at start-up have been used.
FIG. 4 is a circuit diagram of an example of a related-art constant voltage circuit having such a circuit for suppressing inrush current (see, for example, Japanese Patent Laid-Open Publication No. 2003-271251 (Patent Document 1)). FIG. 5 is a graph illustrating a relationship between an output voltage Vout and an output current of the constant voltage circuit of FIG. 4.
In the constant voltage circuit of FIG. 4, an output transistor M101 generates a constant voltage, and the generated constant voltage is output as the output voltage Vout from an output terminal 109. An output current of the output transistor M101 is detected from an output current of a PMOS transistor M102. The PMOS transistor M102 has a gate to which the same voltage as a gate voltage of the output transistor M101 is applied. The output current of the PMOS transistor M102 is input to an output current limiting circuit MA via a switching unit 113.
The output current limiting circuit MA includes a first output current limiting circuit MA1 for limiting current to a first limit current value A1 and a second output current limiting circuit MA2 for limiting current to a second limit current value A2 less than the first limit current value A1.
In response to an ON signal output from an ON/OFF control circuit 111, an error amplifier circuit 101 is activated and the output voltage Vout rises. Upon the rise of the output voltage Vout, the switching unit 113 connects the PMOS transistor M102 to the second output current limiting circuit MA2 for limiting current to the smaller limit current value A2 according to an output signal of a counter circuit 112. Accordingly, a drain current of the PMOS transistor M102 is supplied to the second output current limiting circuit MA2, whereby the output current of the output transistor M101 is limited to the second limit current value A2. This prevents excessive inrush current from flowing from the output terminal 109.
Meanwhile, in response to the ON signal output from the ON/OFF control circuit 111, the counter circuit 112 starts a counting operation. After a certain time period since starting the counting operation, the switching unit 113 connects the PMOS transistor M102 to the first output current limiting circuit MA1 for limiting current to the greater limit current value A1 according to an output signal of the counter circuit 112. Accordingly, during normal operation, the output current of the output transistor M101 is limited to the first limit current value A1 greater than the second limit current value A2.
FIG. 6 is a circuit diagram of another example of a related-art constant voltage circuit (see, for example, Japanese Patent Laid-Open Publication No. 2005-327027 (Patent Document 2)).
In the constant voltage circuit of FIG. 6, an output node of a reference voltage generating circuit 122 is connected to a series circuit of a resistor R123 and a capacitor C121, and a voltage VC at a connection point between the resistor R123 and the capacitor C121 is used as a reference voltage. Accordingly, at start-up of the constant voltage circuit, the capacitor C121 is slowly charged via the resistor 8123 with the reference voltage Vref, so that the voltage VC rises slowly. This reduces high inrush current and overshoot of output voltage.
In the case of the example of FIG. 4, however, if a load resistance connected to the output terminal 109 is small and an output current output from the output terminal 109 is greater than the second limit current value A2, the output voltage Vout rises up to only a voltage level Vc1. Then, after a certain time period, the output voltage Vout rises rapidly to the first limit current value A1 as indicated by the arrow of FIG. 5, which may cause high inrush current.
In the case of the example of FIG. 6, since the voltage VC is derived from the connection between the resistor R123 and the capacitor C121 that are connected in series between the reference voltage Vref and a ground voltage, the accuracy of the voltage VC, which is input to an inverted input node of an error amplifier circuit 121 as the reference voltage, is reduced. Further, since the capacitor C121 is charged via the resistor R123, the charging voltage of the capacitor C121 rapidly rises immediately after start-up. The output voltage Vout is proportional to the charging voltage of the capacitor C121, and hence the output voltage Vout also rapidly rises immediately after start-up, which may cause high inrush current.